There are a number of types of semiconductor devices which depend on high quality oxides or dielectrics for reliable operation.
For example, the gate oxide in a conventional MOSFET device or gate dielectric (gate insulator) in an IGFET device or other gate controlled semiconductor device plays a critical role in device performance, reliability and scaling. In such a device, normally no current flows through the gate dielectric, and high quality oxides or dielectrics, with low trap density and high breakdown field, are required to minimize gate leakage.
However in another class of device (non-volatile memory devices, such as flash memory, a form of EEPROM), the gate dielectric is expected to transport charge when a high electric field is applied. The charge is transferred to a floating gate or to a charge storage layer, where it is stored to provide non-volatile memory capability. Charge is typically injected by applying a high voltage pulse of one polarity and discharged with a high voltage pulse of the opposite polarity. In this case an important parameter is charge-to-breakdown (i.e. the total quantity of charge that can be transported before dielectric breakdown occurs or before the leakage current at low field becomes unacceptably high under such operating conditions). Breakdown may be caused by an accumulation of charge in the gate oxide, which alters the internal electric field, or through the creation of defects, which may themselves be charged and which thus affect subsequent electron transfer. Once electron transport becomes too easy, either runaway occurs and the device breaks down, or the leakage current becomes unacceptably high.
Flash memories are usually made from one of two basic structures, depending upon the nature of the means by which electric charge is stored within the gale structure. In the floating gate structure, charge is stored in (typically) a polysilicon layer that is located between two layers of gate dielectric and is electrically isolated from the rest of the transistor (the “floating” gate). When a high electric field is applied to the gate, some charge is transported to the floating gate (“write” cycle). The presence of the excess charge is detected because it changes the threshold voltage of the MOSFET (the “read” cycle). In the charge storage structure the middle layer of the gate dielectric stack is a material with a smaller bandgap than the surrounding dielectric (e.g. silicon nitride and/or silicon nanocrystals within silicon dioxide). Then a lower field (than for the floating gate structure) is required to deposit charge in the storage layer, where it remains while the MOSFET is held near flat band.
In any of these devices, appropriate selection of gate oxide or other gate dielectric materials with appropriate properties is required for optimum performance.
There are a number of approaches conventionally used to manage device performance and reliability:                Improve oxide quality—i.e. reduce intrinsic impurities, defects and traps that may result in excessive leakage current.        Limit electron energy—electrons pick up energy linearly with distance (ballistic regime) until at a certain point they collide with atoms of the material in which they are travelling, either speed up or slow down, and create defects. Therefore limit the electron energy by using dielectrics with reduced thickness so as to remain in the ballistic regime.        Use another charge storage structure in preference to the floating gate structure, (e.g. SST SuperFlash EEPROM Technology, Technical Paper, Revised March 1999) since a lower electric field ˜4 MV/cm may be used in that case.        
In flash memories that use high voltages, the time of oxide exposure to high electric fields can influence device reliability. Floating gate memory devices may use high electric fields ˜10 MV/cm during erasing. Consequently a great deal of research has gone into alternative materials and structures to improve reliability and lifetime, to enable more read/write cycles. A split gate structure may allow for operation at lower electric fields ˜4 MV/cm (SST SuperFlash EEPROM Technology, Technical Paper, Revised March 1999). Other types of non-volatile memory cells, based on charge trapping, using a charge trapping layer and charge blocking layer, are disclosed, for example, in U.S. Pat. No. 7,525,149 and US patent publication 2008/0217681 which describe particular dielectric materials and structures that may improve device performance and reliability.
Even after applying these strategies most non-volatile memory devices are still sufficiently limited in lifetime that they can only be used in storage applications where a modest number of read/write cycles is expected over the life of the product in which they are used.
Thus, improved or alternative solutions are desirable to overcome the limitations of current gate oxide materials, particularly with respect to charge-to-breakdown and to mitigate hot electron effects for floating gate devices and other semiconductor devices which rely on electron injection and charge transfer and storage.
The present invention seeks to overcome, or ameliorate, one or more of the abovementioned disadvantages, or at least provide an alternative.